Modified floating gate and dielectric layer geometry in 3D memory arrays

US10622450B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Randy J. Koval · Boise, US
• Srikant Jayanti · Boise, US
• Hiroyuki Sanda · Palo Alto, US
• Meng-Wei Kuo · Boise, US
• Srivardhan Gowda · Boise, US
• Krishna K. Parat · Palo Alto, US

Key dates

• Filing date: Jun 28, 2018
• Grant date: Apr 14, 2020
• Expiry date: Jun 28, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/683
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A 3D memory structure including a modified floating gate and dielectric layer geometry is described. In embodiments, a memory cell includes a channel region and a floating gate where a length of the floating gate along a direction of the channel region is substantially longer than a length of the floating gate along an orthogonal direction along the channel region. A control gate adjacent to the floating gate extends at least as long as the control gate along the direction of the channel region and includes a tapered edge extending away from the channel region towards the control gate. In embodiments, a dielectric layer between the control gate and the floating gate may follow the tapered edge along the floating gate and form a discrete region proximate to the floating gate to at least partially insulate the floating gate from an adjacent memory cell. Other embodiments are disclosed and claimed.