System and method of calibrating input signal to successive approximation register (SAR) analog-to-digital converter (ADC) in ADC-assisted time-to- digital converter (TDC)
US10623010B2 · kind B2 · utility
9Cited by
17References
20Claims
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Key dates
| Filing date | Jun 25, 2018 |
| Grant date | Apr 14, 2020 |
| Priority date | — |
| Expiry date | Jun 25, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/183
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus and a method are provided. The apparatus includes an analog-to-digital converter (ADC) driver; and an ADC that is electrically coupled to the ADC driver. The method includes setting, by an analog-to-digital converter (ADC) driver, a desired common-mode control value based on the held voltage; and setting, by the ADC driver, a desired gain control value based on the held voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.