Asymmetric electronic substrate and method of manufacture
US10624213B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2018 |
| Grant date | Apr 14, 2020 |
| Priority date | — |
| Expiry date | Dec 20, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1536
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An asymmetric electronic substrate and method of making the substrate includes forming a first layer on each opposing major surface of a removable carrier layer, the first layer being a routing layer, simultaneously laminating the first layers, and building up subsequent layers on layers previously formed and laminated on the removable carrier layer iteratively. The subsequent layers including routing layers and a core layer formed on each side of the removable carrier layer, the core layer including through holes having a larger gauge than through holes included in the routing layers. A number of layers on a first side of the core layer, between the core layer and the carrier layer, is different than a number of layers on a second side of the core layer. The carrier layer is removed to produce two asymmetric substrates, each asymmetric substrate including one of the at least one core layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.