Inventor · Chandler, AZ, US

Sri Chaitra Jyotsna Chavali

44Patents
4h-index
71Co-inventors
58Inventor score

Filing activity: Jun 25, 2015 → Jan 17, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US10424530B1 Electrical interconnections with improved compliance due to stress relaxation and method of making Electricity 26 Active
US11387175B2 Interposer package-on-package (PoP) with solder array thermal contacts Electricity 5 Active
US9837341B1 Tin-zinc microbump structures Electricity 4 Active
US11158558B2 Package with underfill containment barrier Electricity 4 Active
US9953959B1 Metal protected fan-out cavity Electricity 3 Active
US10685850B2 High density organic interconnect structures Electricity 3 Active
US10424561B2 Integrated circuit structures with recessed conductive contacts for package on package Electricity 2 Active
US10672693B2 Integrated circuit structures in package substrates Electricity 2 Active
US11355849B2 Antenna package using ball attach array to connect antenna and base substrates Electricity 2 Active
US11664290B2 Package with underfill containment barrier Electricity 2 Active
US10624213B1 Asymmetric electronic substrate and method of manufacture Electricity 2 Active
US11869842B2 Scalable high speed high bandwidth IO signaling package architecture and method of making Electricity 1 Active
US11107757B2 Integrated circuit structures in package substrates Electricity 1 Active
US9865568B2 Integrated circuit structures with recessed conductive contacts for package on package Electricity 1 Active
US10658765B2 Edge-firing antenna walls built into substrate Electricity 1 Active
US11430724B2 Ultra-thin, hyper-density semiconductor packages Electricity 1 Active
US12132015B2 Package embedded magnetic inductor structures and manufacturing techniques for 5-50 MHZ SMPS operations Electricity 1 Active
US11804426B2 Integrated circuit structures in package substrates Electricity 0 Active
US11222877B2 Thermally coupled package-on-package semiconductor packages Electricity 0 Active
US11870163B2 Antenna package using ball attach array to connect antenna and base substrates Electricity 0 Active
US12033930B2 Selectively roughened copper architectures for low insertion loss conductive features Electricity 0 Active
US11393762B2 Formation of tall metal pillars using multiple photoresist layers Electricity 0 Active
US10903137B2 Electrical interconnections with improved compliance due to stress relaxation and method of making Electricity 0 Active
US10553453B2 Systems and methods for semiconductor packages using photoimageable layers Electricity 0 Active
US12406914B2 Ultra-thin, hyper-density semiconductor packages Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.