Device, system and process for redundant processor error detection
US10628277B2 · kind B2 · utility
1Cited by
1References
19Claims
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Assignee
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Key dates
| Filing date | Mar 29, 2018 |
| Grant date | Apr 21, 2020 |
| Priority date | — |
| Expiry date | Aug 1, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2236
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, to determine indicators of potential errors in a multi-processing core lockstep computing device comprising a plurality of processing cores, based, at least in part, on observations of output signals generated by at least two processing cores of the plurality of processing cores. A built-in self-test (BIST) procedure may then be based, at least in part, on the determining indicators.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.