Overlapping stacked die package with vertical columns
US10629561B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2019 |
| Grant date | Apr 21, 2020 |
| Priority date | — |
| Expiry date | Feb 22, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18162
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some forms relate to an electronic assembly that includes a die that includes an upper surface and a conductive column extending from the upper surface such that the conductive column is not surrounded by any material other than where the conductive column engages the die. Other forms relate to an electronic package that includes a stack of electronic assemblies where each electronic assembly includes a die that having an upper surface and a plurality of conductive columns extending from the upper surface such that each conductive column is not surrounded by any material other than where the conductive column engages the die, and wherein the stack of electronic assemblies is arranged in an overlapping configuration such the plurality of conductive columns on each electronic assembly are not covered by another electronic assembly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.