Method of manufacturing semiconductor device having stressor
US10629604B2 · kind B2 · utility
0Cited by
8References
15Claims
0Family size
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Key dates
| Filing date | Mar 12, 2019 |
| Grant date | Apr 21, 2020 |
| Priority date | — |
| Expiry date | Mar 12, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0133
Abstract
A semiconductor device includes a substrate, a fin active region pattern on the substrate, the fin active region pattern including an upper region and a lower region, a device isolation layer pattern surrounding the fin active region pattern, a gate pattern on the upper region of the fin active region pattern, and a stressor on the lower region of the fin active region pattern, wherein a top surface of the device isolation layer pattern is lower than a top surface of the upper region and higher than a top surface of the lower region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.