Memory device

US10629612B2 · kind B2 · utility

Assignee

• TOSHIBA MEMORY CORPORATION · JP

Inventors

• Takamasa Okawa · Yokkaichi, JP
• Tetsuji Kunitake · Numazu, JP
• Takuji Kanebishi · Yokkaichi, JP
• Yusuke Takagi · Hitachinaka, JP

Key dates

• Filing date: Jul 30, 2018
• Grant date: Apr 21, 2020
• Expiry date: Jul 30, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/35

Abstract

A memory device includes first to third electrode layers and first to third columnar bodies. The first electrode layers are stacked above a foundation layer. The second and third electrode layers are arranged above the first electrode layers in a direction crossing a stacking direction of the first electrode layers. The first columnar body extends through the first and second electrode layers. The second columnar body extends through the first and third electrode layers. The third columnar body extends through the first electrode layers, and is positioned between the second electrode layer and the third electrode layer. The first to third columnar bodies include first to third semiconductor layers, respectively. The first and second semiconductor layers are electrically connected to the foundation layer, and the third semiconductor layer is electrically insulated from the foundation layer by an insulating film provided between the foundation layer and the third semiconductor layer.