Mid-cycle adjustment of internal clock signal timing
US10631248B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2017 |
| Grant date | Apr 21, 2020 |
| Priority date | — |
| Expiry date | Nov 8, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/70
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Changes in operating conditions, like voltage or temperature, can cause the frequency of an internal clock signal to change and negatively affect device operation. In one embodiment, a method for controlling internal clock frequency of a device includes counting a number of clock cycles of the internal clock signal relative to a current period of a system clock signal to determine a current mid-cycle count of clock cycles, wherein the internal clock signal is based on a first clock signal of a plurality of clock signals produced in the device, each having a different frequency. When the current mid-cycle count is differs from a calibrated mid-cycle count by more than a tolerable amount, a second clock signal of the plurality of clock signals is selected as the internal clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.