Anand Seshadri
34Patents
8h-index
28Co-inventors
75Inventor score
Filing activity: Oct 8, 1997 → Oct 29, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9741724B2 | SRAM well-tie with an uninterrupted grated first poly and first contact patterns in a bit cell array | Electricity | 25 | Active |
| US7133304B2 | Method and apparatus to reduce storage node disturbance in ferroelectric memory | Physics | 24 | Expired |
| US6730950B1 | Local interconnect using the electrode of a ferroelectric | Electricity | 23 | Expired |
| US8325511B2 | Retain-till-accessed power saving mode in high-performance static memories | Physics | 19 | Active |
| US6980459B2 | Non-volatile SRAM | Physics | 18 | Expired |
| US8218376B2 | Reduced power consumption in retain-till-accessed static memories | Physics | 17 | Active |
| US6091114A | Method and apparatus for protecting gate oxide from process-induced charging effects | Electricity | 13 | Expired |
| US6965520B1 | Delay system for generating control signals in ferroelectric memory devices | Physics | 9 | Expired |
| US8560931B2 | Low power retention random access memory with error correction on wake-up | Electricity | 8 | Active |
| US6103561A | Depletion mode MOS capacitor with patterned V.sub.T implants | Electricity | 8 | Expired |
| US5986314A | Depletion mode MOS capacitor with patterned V.sub.t implants | Electricity | 7 | Expired |
| US7200027B2 | Ferroelectric memory reference generator systems using staging capacitors | Physics | 5 | Expired |
| US7301795B2 | Accelerated low power fatigue testing of FRAM | Physics | 4 | Expired |
| US7985990B2 | Transistor layout for manufacturing process control | Electricity | 3 | Active |
| US9576621B2 | Read-current and word line delay path tracking for sense amplifier enable timing | Physics | 3 | Active |
| US8971138B2 | Method of screening static random access memory cells for positive bias temperature instability | Physics | 3 | Active |
| US8394681B2 | Transistor layout for manufacturing process control | Electricity | 3 | Active |
| US8654562B2 | Static random access memory cell with single-sided buffer and asymmetric construction | Electricity | 3 | Active |
| US8159863B2 | 6T SRAM cell with single sided write | Physics | 2 | Active |
| US6348370B1 | Method to fabricate a self aligned source resistor in embedded flash memory applications | Electricity | 2 | Expired |
| US8301431B2 | Apparatus and method for accelerating simulations and designing integrated circuits and other systems | Physics | 2 | Active |
| US8184474B2 | Asymmetric SRAM cell with split transistors on the strong side | Physics | 2 | Active |
| US8724375B2 | SRAM cell having an N-well bias | Physics | 2 | Active |
| US10631248B2 | Mid-cycle adjustment of internal clock signal timing | Emerging Cross-Sectional Technologies | 2 | Active |
| US8379434B2 | SRAM cell for single sided write | Physics | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.