On-chip copy with data folding in three-dimensional non-volatile memory array
US10635585B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2018 |
| Grant date | Apr 28, 2020 |
| Priority date | — |
| Expiry date | Jan 17, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an on-chip copy process, performed by a storage device, data is copied from a plurality of Single Level Cell (SLC) blocks of non-volatile three-dimensional memory (e.g., 3D flash memory) in a respective memory die to a Multilevel Cell (MLC) block of the same memory die. A copy of source data from a respective SLC block is interleaved with a copy of source data from one or more other SLC blocks in the memory die to produce interleaved source data. Each source data copy that is interleaved is rotated by an offset assigned to the respective SLC block from which the source data is copied, and each respective SLC block in the plurality of SLC blocks is assigned a distinct offset. Each distinct set of the interleaved source data is written to a distinct respective MLC page of the MLC block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.