Safe double buffering using DMA safe linked lists
US10635615B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2019 |
| Grant date | Apr 28, 2020 |
| Priority date | — |
| Expiry date | Jan 25, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A first sequence of transaction control sets (TCSs) collectively describe a first data transfer by which first data is to be moved between a first peripheral and first and second memory buffers. A first portion of the first data is transferred between the first memory buffer and the first peripheral according to a first TCS in the first sequence. Subsequently, a second portion of the first data is transferred between the second memory buffer and the first peripheral according to a second TCS in the first sequence. An actual error detection code is determined based on the first and/or second portions of the first data or an address actually processed during execution of the first and/or second TCSs. An error is selectively flagged based on whether the actual error detection code is the same as an expected error detection code contained in a third TCS in the first sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.