Glitch detection at clock domain crossing

US10635767B2 · kind B2 · utility

Assignee

• MENTOR GRAPHICS CORPORATION · US

Inventors

• Sulabh Kumar Khare · Noida, IN
• Ashish Hari · Noida, IN

Key dates

• Filing date: Jan 31, 2018
• Grant date: Apr 28, 2020
• Expiry date: May 8, 2038

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2119/12
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

This application discloses a computing system to perform one or more static checks on clock domain crossings in a circuit design to detect combinational logic configured to generate output signals having glitches that cross clock domains in a circuit design. The computing system can identify the combinational logic is configured to generate the output signal based, at least in part, on an input signal and an inversion of the input signal. The computing system can identify conditions that, when satisfied, allow the combinational logic to generate the output signal based, at least in part, on the input signal and the inversion of the input signal, and generate a glitch expression based, at least in part, on the identified conditions. The computing system can determine the combinational logic is configured to generate at least one glitch in the output signal based, at least in part, on the glitch expression.