Memory device including alignment mark trench
US10636744B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2018 |
| Grant date | Apr 28, 2020 |
| Priority date | — |
| Expiry date | Aug 9, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory device includes an insulation layer, an interconnection structure disposed in the insulation layer, a dielectric layer disposed on the insulation layer and the interconnection structure, a connection hole disposed on the interconnection structure and penetrates the dielectric layer, an alignment mark trench penetrating the dielectric layer on a peripheral region, a first patterned conductive layer, and a patterned memory material layer. The first patterned conductive layer includes a connection structure at least partly disposed in the connection hole and a first pattern disposed in the alignment mark trench. The patterned memory material layer includes a first memory material pattern disposed on the connection structure and a second memory material pattern disposed in the alignment mark trench. Manufacturing yield and alignment condition of forming the memory device may be improved by disposing a part of the first patterned conductive layer in the alignment mark trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.