Semiconductor packages
US10636760B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2018 |
| Grant date | Apr 28, 2020 |
| Priority date | — |
| Expiry date | Jul 25, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package may include a base layer, and a redistribution layer on the base layer. The semiconductor package may include a first pattern, a second pattern, and a passivation layer covering the first and second patterns. The semiconductor package may include a semiconductor chip on the base layer, a first connection terminal between the base layer and the semiconductor chip and coupled to one of chip pads of the semiconductor chip, and a mold layer between the base layer and the semiconductor chip. The first connection terminal may extend into the passivation layer and may be coupled to the first pattern. The second pattern may be electrically insulated from the semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.