Three-dimensional memory devices having transferred interconnect layer and methods for forming the same
US10636813B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 26, 2019 |
| Grant date | Apr 28, 2020 |
| Priority date | — |
| Expiry date | Jun 26, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B53/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a method for forming a 3D memory device is disclosed. A memory stack including interleaved sacrificial layers and dielectric layers is formed above a first substrate. A channel structure extending vertically through the memory stack is formed. A single-crystal silicon layer is formed in a second substrate. An interconnect layer including a bit line is formed on the single-crystal silicon layer above the second substrate. The single-crystal silicon layer and the interconnect layer formed thereon are transferred from the second substrate onto the memory stack above the first substrate, such that the bit line in the interconnect layer is electrically connected to the channel structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.