Isolation regions for reduced junction leakage
US10636870B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2018 |
| Grant date | Apr 28, 2020 |
| Priority date | — |
| Expiry date | Aug 15, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure describes a fabrication method that prevents divots during the formation of isolation regions in integrated circuit fabrication. In some embodiments, the method of forming the isolation regions includes depositing a protective layer over a semiconductor layer; patterning the protective layer to expose areas of the semiconductor layer; depositing an oxide on the exposed areas the semiconductor layer and between portions of the patterned protective layer; etching a portion of the patterned protective layer to expose the semiconductor layer; etching the exposed semiconductor layer to form isolation openings in the semiconductor layer; and filling the isolation openings with a dielectric to form the isolation regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.