Apparatus and method to prevent integrated circuit from entering latch-up mode
US10636872B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2018 |
| Grant date | Apr 28, 2020 |
| Priority date | — |
| Expiry date | Oct 31, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/854
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The disclosure provides an apparatus for preventing an integrated circuit (IC) structure from entering a latch-up mode. In an embodiment, the apparatus may include: a p-type substrate; an n-well within the p-type substrate; an n-type region within the p-type substrate, the n-type region being distinct from the n-well; a p-type region within the n-well; a power supply electrically coupled to the p-type region within the n-well; and a directional diode electrically coupling the power supply to the n-well in parallel with the p-type region. The directional diode biases a current flow from the power supply to the n-well, and the directional diode contacts the n-well distal to the p-type region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.