Method of manufacturing a semiconductor device and a semiconductor device
US10636891B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2018 |
| Grant date | Apr 28, 2020 |
| Priority date | — |
| Expiry date | Nov 21, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. A first insulating layer is formed, in the source/drain space, at least on etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space, thereby forming air gaps between the source/drain epitaxial layer and the first semiconductor layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.