Methodology and structure for field plate design
US10636904B2 · kind B2 · utility
6Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2018 |
| Grant date | Apr 28, 2020 |
| Priority date | — |
| Expiry date | Mar 21, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/378
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure, in some embodiments, relates to a transistor device having a field plate. The transistor device has a gate electrode disposed over a substrate between a source region and a drain region. One or more dielectric layers are arranged over the gate electrode, and a field plate is arranged over the one or more dielectric layers. The field plate extends from a first outermost sidewall that is directly over an upper surface of the gate electrode to a second outermost sidewall that is between the gate electrode and the drain region and that extends to below the upper surface of the gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.