Yu-Chang Jong
43Patents
7h-index
58Co-inventors
72Inventor score
Filing activity: Sep 17, 2001 → Aug 4, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9590053B2 | Methodology and structure for field plate design | Electricity | 19 | Active |
| US7372083B2 | Embedded silicon-controlled rectifier (SCR) for HVPMOS ESD protection | Electricity | 12 | Active |
| US7129559B2 | High voltage semiconductor device utilizing a deep trench structure | Electricity | 11 | Expired |
| US7808069B2 | Robust structure for HVPW Schottky diode | Electricity | 9 | Active |
| US9954097B2 | Methodology and structure for field plate design | Electricity | 8 | Active |
| US7081662B1 | ESD protection device for high voltage | Electricity | 8 | Expired |
| US8344416B2 | Integrated circuits using guard rings for ESD, systems, and methods for forming the integrated circuits | Electricity | 7 | Active |
| US10636904B2 | Methodology and structure for field plate design | Electricity | 6 | Active |
| US7521741B2 | Shielding structures for preventing leakages in high voltage MOS devices | Electricity | 6 | Active |
| US6943062B2 | Contaminant particle removal by optical tweezers | Emerging Cross-Sectional Technologies | 6 | Expired |
| US6623911B1 | Method to form code marks on mask ROM products | Electricity | 5 | Expired |
| US9666574B1 | Semiconductor device structure and manufacturing method thereof | Electricity | 4 | Active |
| US11164970B2 | Contact field plate | Electricity | 3 | Active |
| US9748361B2 | Integrated circuits using guard rings for ESD systems, and methods for forming the integrated circuits | Electricity | 3 | Active |
| US7482662B2 | High voltage semiconductor device utilizing a deep trench structure | Electricity | 3 | Active |
| US7384802B2 | ESD protection device for high voltage | Electricity | 2 | Active |
| US9634154B1 | Schottky diode having a well with peripherial cathod regions and center andoe region | Electricity | 2 | Active |
| US8004038B2 | Suppression of hot-carrier effects using double well for thin gate oxide LDMOS embedded in HV process | Electricity | 2 | Active |
| US10861946B1 | Field plate structure for high voltage device | Electricity | 2 | Active |
| US10756208B2 | Integrated chip and method of forming the same | Electricity | 2 | Active |
| US11121225B2 | Field plate structure to enhance transistor breakdown voltage | Electricity | 1 | Active |
| US10964810B2 | Methodology and structure for field plate design | Electricity | 1 | Active |
| US8772092B2 | Integrated circuits using guard rings for ESD, systems, and methods for forming the integrated circuits | Electricity | 1 | Active |
| US12426296B2 | High-voltage semiconductor devices and methods of formation | Electricity | 0 | Active |
| US11398467B2 | Methods for forming integrated circuit having guard rings | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.