Semiconductor structure and method of forming the same

US10636961B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Harry-Hak-Lay Chuang · Austin, US
• Hsia-Wei Chen · Taipei, TW
• Hung Cho Wang · Taipei, TW
• Kuei-Hung Shen · Hsinchu, TW

Key dates

• Filing date: Dec 7, 2017
• Grant date: Apr 28, 2020
• Expiry date: Dec 7, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N50/85

Abstract

The present disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a memory region. The memory region comprises a bottom via, a recap layer on the BV, a bottom electrode on the recap layer, a magnetic tunneling junction layer on the bottom electrode, and a top electrode on the MTJ layer. The material of the recap layer is different from that of the BV.