Digital calibration of capacitive mismatches in analog-to-digital converters
US10637493B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2019 |
| Grant date | Apr 28, 2020 |
| Priority date | — |
| Expiry date | Mar 22, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/125
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for calibrating a CDAC-based analog-to-digital converter is disclosed. In one aspect, a calibration method includes: applying a predetermined pattern of voltages to first plates of a group of N capacitors, wherein N is an integer greater than 1; applying a zero voltage to the second plates of the group of N capacitors, wherein the second plates of the group of N capacitors are connected in common; removing the zero voltage to the second plates of the group of N capacitors; applying a zero voltage to all of the first plates of the group of N capacitors; quantizing a voltage on the second plates of the group of N capacitors; converting the quantized voltage on the second plates of the group of N capacitors to an adjustment value; and loading the adjustment value into a lookup table.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.