Register access in a distributed memory buffer system
US10642535B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2018 |
| Grant date | May 5, 2020 |
| Priority date | — |
| Expiry date | May 13, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1051
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system, architecture, and method for storing data in response to commands received from a host is disclosed. The memory system includes a memory control circuit configured to receive commands from the host; at least one memory device configured to store data; and at least one data buffer circuit associated with the at least one memory device and the memory control circuit, the data buffer circuit having data buffers and at least one register. The system preferably includes communication links between the host, the at least one memory control circuit, the at least one data buffer circuit, and the at least one memory device. The system preferably is configured so that register access commands are sent by the host to the memory control circuit over the communication links between the host and the memory control circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.