Memory controller for flash memory with zones configured on die bounaries and with separate spare management per zone
US10642748B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2017 |
| Grant date | May 5, 2020 |
| Priority date | — |
| Expiry date | Aug 29, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7205
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.