Multi-core processor and operation method thereof
US10642782B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2017 |
| Grant date | May 5, 2020 |
| Priority date | — |
| Expiry date | Jun 20, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-core processor having a first operation mode in which processors perform the same task and a second operation mode in which the processors perform different tasks includes first and second processors configured to write an operation mode value to a first register or second register when a function called in executed software requests the first or second operation mode, a manager configured to assign core IDs of the first and second processors according to the operation mode value stored in the first register or second register, and a reset controller configured to reset the first and second processors in response to the function, wherein the manager assigns the same core ID to the first and second processors when the operation mode value indicates the first operation mode, and allocates different core IDs to the first and second processors when the operation mode value indicates the second operation mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.