Semiconductor memory device
US10643704B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2018 |
| Grant date | May 5, 2020 |
| Priority date | — |
| Expiry date | Sep 17, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory structural body including first and second planes each of which includes memory cells coupled to word lines extending in a first direction and bit lines extending in a second direction and which are disposed along the first direction; and a logic structural body disposed between a substrate and the memory structural body, and including a row decoder. The row decoder includes a pass transistor circuit which is coupled in common to the first and second planes and a block switch circuit which controls the pass transistor circuit. The block switch circuit is disposed in first and second plane regions of the logic structural body which overlap with the first and second planes in a third direction perpendicular to the first and second directions, and the pass transistor circuit is disposed in an interval region between the first and second plane regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.