Method for operating low-current EEPROM array
US10643708B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2018 |
| Grant date | May 5, 2020 |
| Priority date | — |
| Expiry date | Oct 12, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for operating a low-current EEPROM array is disclosed. The EEPROM array comprises bit line groups, word lines, common source lines, and sub-memory arrays. Each sub-memory array includes a first memory cell and a second memory cell. The first memory cell is connected with one bit line of a first bit line group, a first common source line, and a first word line. The second memory cell is connected with the other bit line of the first bit line group, the first common source line, and a second word line. The first and second memory cells are operation memory cells and symmetrically arranged at two sides of the first common source line. The method uses special biases to perform the bytes writing and erasing with low current, low voltage and low cost.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.