3D memory having plural lower select gates
US10644018B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2018 |
| Grant date | May 5, 2020 |
| Priority date | — |
| Expiry date | Jun 23, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A 3D NAND memory on a single integrated circuit is described including a block of vertical NAND strings, including a plurality of sub-blocks. Sub-blocks in the plurality of sub-blocks each comprise an upper select line in an upper level; word lines in intermediate levels below the upper level; a first lower select line in a first lower level below the intermediate levels; a second lower select line in a second lower level below the first lower level. A reference conductor can be disposed below the block. Bit lines are disposed over the block. Control circuitry applies voltages to the upper select lines, to the word lines and to the first and second lower select lines in the plurality of sub-blocks in various combinations for memory operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.