Three-dimensional semiconductor memory device with a substrate contact region and method of manufacturing the same

US10644020B2 · kind B2 · utility

Assignee

• INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES · CN

Inventors

• Zongliang Huo · 红钢城街道, CN
• Tianchun Ye · Beijing, CN

Key dates

• Filing date: Nov 23, 2015
• Grant date: May 5, 2020
• Expiry date: Nov 23, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B41/27

Abstract

A three-dimensional semiconductor device includes: A peripheral circuit, distributed on a substrate; a plurality of memory cells above the peripheral circuit, each of which includes: a common source region, between the memory cell and the peripheral circuit; a channel layer, distributed in a direction perpendicular to the surface of the substrate; at least one substrate contact layer, extending horizontally from the central portion of the channel layer parallel to the surface of the substrate, each comprising at least one substrate contact region; a plurality of insulating layers, located on sidewalls of the channel layer; a plurality of control gates, sandwiched between adjacent insulating layers; a gate dielectric layer, located between the channel layer and the control gates; a drain region, located at top of the channel layer; a substrate contact lead-out line, electrically connected to the substrate contact regions; and a bit line wiring, electrically connected to the drain region of each memory cell and the peripheral circuit. The substrate contact regions are formed in the middle of the memory strings, improving the erase/write performance and reliability of the memory, incr…