Apparatus and methods for accurate latency measurements in integrated circuits
US10649486B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2016 |
| Grant date | May 12, 2020 |
| Priority date | — |
| Expiry date | Dec 15, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0682
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
One embodiment relates to a method of performing a latency measurement within an integrated circuit. Receipt of a word that contains a beginning of a frame is detected by a frame begin detect circuit in a decoding circuit block. A begin frame detected signal is fed back to the physical media attachment circuit, and an asynchronous signal from the physical media attachment circuit is transmitted at a beginning of a subsequent frame to a time measurement circuit in a core of the integrated circuit. A bitcount may be used to generate a synchronous signal that is also transmitted to the core. At the core of the integrated circuit, a first time is measured that corresponds to receipt of the asynchronous signal and a second time is measured that corresponds to receipt of the synchronous signal. A latency is determined at least by subtracting the first time subtracted from the second time. Other embodiments and features are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.