Processors supporting atomic writes to multiword memory locations and methods
US10649773B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2016 |
| Grant date | May 12, 2020 |
| Priority date | — |
| Expiry date | Dec 8, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/452
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method process atomic instructions. A processor system includes a load store unit (LSU), first and second registers, a memory interface, and a main memory. In response to a load link (LL) instruction, the LSU loads first data from memory into the first register and sets an LL bit (LLBIT) to indicate a sequence of atomic instructions is being executed. The LSU further loads second data from memory into the second register in response to a load (LD) instruction. The LSU places a value of the second register into the memory interface in response to a store conditional coupled (SCX) instruction. When the LLBIT is set and in response to a store (SC) instruction, the LSU places a value of the second register into the memory interface and commits the first and second register values in the memory interface into the main memory when the LLBIT is set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.