Electrical mask validation
US10650111B2 · kind B2 · utility
1Cited by
9References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2017 |
| Grant date | May 12, 2020 |
| Priority date | — |
| Expiry date | Nov 30, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of the invention may include a method for ensuring semiconductor design integrity. The method may include analyzing a photomask design for a semiconductor circuit. The photomask may include a primary electrical design necessary for the operation of the semiconductor circuit, and white space, which has no primary electrical design. The method may include inserting a secondary electrical design into the white space of the photomask design for the semiconductor circuit. The secondary electrical design may have known electrical properties for validating the semiconductor circuit design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.