Energy efficient phase change random access memory cell array write via controller-side aggregation management
US10650889B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 14, 2018 |
| Grant date | May 12, 2020 |
| Priority date | — |
| Expiry date | Dec 14, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0085
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a memory controller; and a memory device including a memory cell array, which includes a plurality of bit lines and a plurality of blocks. Each block includes a plurality of word lines, and each word line includes a plurality of phase-change random access memory (PRAM) cells connected, respectively, to the plurality of bit lines. The memory controller is configured to buffer write requests each including write data and is configured to perform a write operation that includes a reset phase and a subsequent set phase. The reset phase includes erasing the PRAM cells included in first word lines from among the plurality of word lines included in a selected block, from among the plurality of blocks, and the set phase includes, after the reset phase, writing the write data from the buffered write requests to the PRAM cells of the first word lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.