Semiconductor fault analysis device and fault analysis method thereof
US10650910B2 · kind B2 · utility
2Cited by
13References
20Claims
0Family size
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Key dates
| Filing date | Jan 16, 2019 |
| Grant date | May 12, 2020 |
| Priority date | — |
| Expiry date | Jan 16, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5606
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fault analysis method of a semiconductor fault analysis device is provided. The fault analysis method includes: receiving measurement data measured corresponding to a semiconductor device; generating double sampling data based on the measurement data and reference data; performing a fault analysis operation with respect to the double sampling data; classifying a fault type of the semiconductor device based on a result of the fault analysis operation; and outputting information about the fault type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.