Integrated circuit (IC) interconnect structure having a metal layer with asymmetric metal line-dielectric structures supporting self-aligned vertical interconnect accesses (VIAS)
US10651122B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2019 |
| Grant date | May 12, 2020 |
| Priority date | — |
| Expiry date | Feb 18, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76804
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) interconnect structure may include a metal layer with asymmetric metal line-dielectric structures supporting fully self-aligned vertical interconnect accesses (vias). The interconnect structure includes metal lines spaced at a metal line pitch and dielectric structures disposed between adjacent metal lines. The width of the metal lines is asymmetric to the width of dielectric structures, providing an asymmetric width relationship that allows a metal line to have a greater cross-sectional area for reducing electrical resistance without having to increase metal line pitch. The via pattern is self-aligned to an upper metal opening at the top and an underlayer metal recess opening at the bottom, allowing the maximum contact area to reduce via resistance. To reduce capacitive coupling between adjacent metal lines, the adjacent interconnect structures include a plurality of gaps formed in a dielectric material of the dielectric structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.