Manufacturing method of semiconductor device
US10651183B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2018 |
| Grant date | May 12, 2020 |
| Priority date | — |
| Expiry date | Dec 14, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/44
Abstract
A manufacturing method of a semiconductor device includes: providing a substrate having memory and high voltage regions; sequentially forming a floating gate layer and a hard mask layer on the substrate; patterning the hard mask layer to form a first opening exposing a portion of the floating gate layer in the range of the memory region; patterning the hard mask layer and the floating gate layer to form a second opening overlapped with the high voltage region; performing a first thermal growth process to simultaneously form a first oxide structure on the portion of the floating gate layer exposed by the first opening, and to form a second oxide structure on a portion of the substrate overlapped with the second opening; removing the hard mask layer; and patterning the floating gate layer by using the first oxide structure as a mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.