Patent · US Active

Word line structure of three-dimensional memory device

US10651192B2 · kind B2 · utility

4Cited by
7References
16Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJul 26, 2018
Grant dateMay 12, 2020
Priority date
Expiry dateJul 26, 2038

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L23/53257
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate, a first tier of conductor layers of a first length comprising a first plurality of conductor layers extending along a first direction over the substrate. The first direction is substantially parallel to a top surface of the substrate. In some embodiments, the memory device also includes at least one connection portion conductively connecting two or more conductor layers of the first tier, and a first metal contact via conductively shared by connected conductor layers of the first tier and connected to a first metal interconnect.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.