Three-dimensional semiconductor memory device
US10651195B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2018 |
| Grant date | May 12, 2020 |
| Priority date | — |
| Expiry date | Oct 23, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
Abstract
A three-dimensional semiconductor memory device includes an electrode structure including gate electrodes and insulating layers, which are alternately stacked on a substrate, a semiconductor pattern extending in a first direction substantially perpendicular to a top surface of the substrate and penetrating the electrode structure, a tunnel insulating layer disposed between the semiconductor pattern and the electrode structure, a blocking insulating layer disposed between the tunnel insulating layer and the electrode structure, and a charge storing layer disposed between the blocking insulating layer and the tunnel insulating layer. The charge storing layer includes a plurality of first charge trap layers having a first energy band gap, and a second charge trap layer having a second energy band gap larger than the first energy band gap. The first charge trap layers are embedded in the second charge trap layer between the gate electrodes and the semiconductor pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.