Integrated circuit including interconnection and method of fabricating the same, the interconnection including a pattern shaped and/or a via disposed for mitigating electromigration
US10651201B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2018 |
| Grant date | May 12, 2020 |
| Priority date | — |
| Expiry date | Jun 13, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/985
Abstract
An integrated circuit includes a first conductive pattern in a first conductive layer, a second conductive pattern in a second conductive layer over the first conductive layer, and a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern to pass through at different times. The via is placed on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.