Digital alloy based back barrier for P-channel nitride transistors
US10651306B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2017 |
| Grant date | May 12, 2020 |
| Priority date | — |
| Expiry date | Aug 25, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
Abstract
A III-nitride power handling device and the process of making the III-nitride power handling device are disclosed that use digital alloys as back barrier layer to mitigate the strain due to lattice mismatch between the channel layer and the back barrier layer and to provide increased channel conductivity. An embodiment discloses a GaN transistor using a superlattice binary digital alloy as back barrier comprising alternative layers of AlN and GaN. Other embodiments include using superlattice structures with layers of GaN and AlGaN as well as structures using AlGaN/AlGaN stackups that have different Aluminum concentrations. The disclosed device has substantially increased channel conductivity compared to traditional analog alloy back barrier devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.