V-shape recess profile for embedded source/drain epitaxy
US10651309B2 · kind B2 · utility
0Cited by
19References
20Claims
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Key dates
| Filing date | Jul 30, 2018 |
| Grant date | May 12, 2020 |
| Priority date | — |
| Expiry date | Jul 30, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/151
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a semiconductor base. A dielectric isolation structure is formed in the semiconductor base. A source/drain of a FinFET transistor is formed on the semiconductor base. A bottom segment of the source/drain is embedded into the semiconductor base. The bottom segment of the source/drain has a V-shaped cross-sectional profile. The bottom segment of the source/drain is separated from the dielectric isolation structure by portions of the semiconductor base.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.