Tzu-Ching Lin
25Patents
3h-index
20Co-inventors
59Inventor score
Filing activity: Dec 9, 2010 → Jul 19, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10453943B2 | FETS and methods of forming FETS | Electricity | 10 | Active |
| US10038095B2 | V-shape recess profile for embedded source/drain epitaxy | Electricity | 8 | Active |
| US9905641B2 | Semiconductor device and manufacturing method thereof | Electricity | 4 | Active |
| US10867861B2 | Fin field-effect transistor device and method of forming the same | Electricity | 3 | Active |
| US10510607B1 | Semiconductor device convex source/drain region | Electricity | 2 | Active |
| US8771558B2 | Method of manufacturing anti-counterfeit ink and anti-counterfeit tag and method of manufacturing the same | Performing Operations; Transporting | 2 | Active |
| US10950730B2 | Merged source/drain features | Electricity | 2 | Active |
| US11004725B2 | Method of forming a FinFET device with gaps in the source/drain region | Electricity | 1 | Active |
| US11205713B2 | FinFET having a non-faceted top surface portion for a source/drain region | Electricity | 1 | Active |
| US11355641B2 | Merged source/drain features | Electricity | 1 | Active |
| US11823949B2 | FinFet with source/drain regions comprising an insulator layer | Electricity | 1 | Active |
| US10468482B2 | Semiconductor device and manufacturing method thereof | Electricity | 1 | Active |
| US12243784B2 | Silicon phosphide semiconductor device | Electricity | 0 | Active |
| US11121255B2 | V-shape recess profile for embedded source/drain epitaxy | Electricity | 0 | Active |
| US11961912B2 | Merged source/drain features | Electricity | 0 | Active |
| US11069578B2 | Method of manufacturing a semiconductor device | Electricity | 0 | Active |
| US10763366B2 | V-shape recess profile for embedded source/drain epitaxy | Electricity | 0 | Active |
| US12402344B2 | FETS and methods of forming FETS | Electricity | 0 | Active |
| US11004745B2 | Semiconductor device convex source/drain region | Electricity | 0 | Active |
| US10991630B2 | Semiconductor device and method | Electricity | 0 | Active |
| US11749567B2 | Silicon phosphide semiconductor device | Electricity | 0 | Active |
| US11600715B2 | FETs and methods of forming FETs | Electricity | 0 | Active |
| US10651309B2 | V-shape recess profile for embedded source/drain epitaxy | Electricity | 0 | Active |
| US10991795B2 | Semiconductor device and manufacturing method thereof | Electricity | 0 | Active |
| US11127637B2 | Semiconductor device convex source/drain region | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.