Memory device and fabrication method thereof
US10651373B2 · kind B2 · utility
4Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2018 |
| Grant date | May 12, 2020 |
| Priority date | — |
| Expiry date | Nov 16, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
Abstract
A method for forming an integrated circuit is provided. The method includes forming a dielectric layer over a cell region and a logic region of a substrate; forming a resistance switching layer over the dielectric layer; performing at least one etch process to pattern the resistance switching layer into a plurality of resistance switching elements in the cell region, in which a first portion of the dielectric layer in the logic region is less etched by the etch process than a second portion of the dielectric layer in the cell region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.