Low voltage tolerant ultra-low power edge triggered flip-flop for standard cell library
US10651850B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2019 |
| Grant date | May 12, 2020 |
| Priority date | — |
| Expiry date | Mar 25, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0185
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and a flip-flop for designing low power integrated circuits (IC's). The method includes receiving at least one of a clock signal, a data signal, and a complimentary data signal. The complimentary data signal is produced by an input data inverter present in the flip-flop. Further, the method includes generating at least one master internal signal based on the received at least one of the clock signal, the data signal, and the complimentary data signal, when the clock signal is at a low logic level. Further, the method includes generating at least one slave internal signal based on at least one of the received clock signal and the generated at least one master internal signal, when the clock signal is at a high logic level. Further, the method includes generating an output signal based on the generated at least one slave internal signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.