Timing insulation circuitry for partial reconfiguration of programmable integrated circuits
US10651853B1 · kind B1 · utility
7Cited by
42References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 23, 2019 |
| Grant date | May 12, 2020 |
| Priority date | — |
| Expiry date | May 23, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1776
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A device includes a platform implemented in programmable circuitry of the device. The platform is configured to communicate with a host data processing system. The device includes a first partial reconfiguration region implemented in the programmable circuitry and coupled to the platform. The first partial reconfiguration region is reserved for implementing user-specified circuitry. The device includes timing insulation circuitry implemented in the programmable circuitry and configured to isolate timing of signals passing between the platform and the first partial reconfiguration region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.