Locking a PLL to the nearest edge of the input clock when the input clock is divided down before use in the PLL
US10651862B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2019 |
| Grant date | May 12, 2020 |
| Priority date | — |
| Expiry date | Jun 14, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop (PLL) has a first divider that receives a first reference clock signal and supplies a first divided reference clock signal. A second divider receives a second reference clock signal and supplies a second divided reference clock signal. On switching between use of reference clock signals, when the phase difference between the first divided signal and the second divided signal includes one or more clock periods of the second reference clock signal, the PLL performs a phase adjust to remove the one or more clock periods. The phase adjust can be performed in the feedback divider or as an offset in the loop if digital edges of the clock signals are available. The phase adjust ensures the phase adjust on the PLL output caused by switching reference clocks is the phase difference between the reference clock signals before division.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.