Inventor · Austin, TX, US

James D. Barnette

20Patents
7h-index
19Co-inventors
66Inventor score

Filing activity: Feb 7, 1997 → Nov 18, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US6055619A Circuits, system, and methods for processing multiple data streams Physics 171 Expired
US6970511B1 Interpolator, a resampler employing the interpolator and method of interpolating a signal associated therewith Electricity 83 Expired
US10727845B1 Use of a virtual clock in a PLL to maintain a closed loop system Electricity 26 Active
US10951216B1 Synchronization of clock signals generated using output dividers Electricity 17 Active
US8923341B2 Method for switching master/slave timing in a 1000BASE-T link without traffic disruption Electricity 10 Active
US11038521B1 Spur and quantization noise cancellation for PLLS with non-linear phase detection Electricity 8 Active
US10826507B1 Fractional divider with error correction Electricity 7 Active
US10608649B1 Relative frequency offset error and phase error detection for clocks Electricity 6 Active
US10727844B1 Reference clock frequency change handling in a phase-locked loop Electricity 6 Active
US6973146B1 Resampler for a bit pump and method of resampling a signal associated therewith Electricity 6 Expired
US10819354B2 Accurate and reliable digital PLL lock indicator Electricity 2 Active
US7542536B2 Resampler for a bit pump and method of resampling a signal associated therewith Electricity 2 Expired
US11245406B2 Method for generation of independent clock signals from the same oscillator Electricity 2 Active
US10693475B1 Gradual frequency transition with a frequency step Electricity 2 Active
US10651862B1 Locking a PLL to the nearest edge of the input clock when the input clock is divided down before use in the PLL Electricity 2 Active
US11526135B2 Using time-to-digital converters to delay signals with high accuracy and large range Electricity 1 Active
US11342926B2 Synchronization of clock signals generated using output dividers Electricity 0 Active
USRE48130E1 Method for switching master/slave timing in a 1000Base-T link without traffic disruption General 0 Active
US8179901B2 System and method for squelching a recovered clock in an ethernet network Electricity 0 Active
US12019406B2 Using time-to-digital converters to delay signals with high accuracy and large range Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.