Method and apparatus to provide both high speed and low speed signaling from the high speed transceivers on an field programmable gate array
US10652131B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2014 |
| Grant date | May 12, 2020 |
| Priority date | — |
| Expiry date | Sep 12, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B14/026
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device, such as a field programmable gate array (FPGA), is disclosed that allows for both high speed and low speed signal processing using the existing high speed transceiver. The programmable logic of the device may be programmed to include a sampling logic block that determines the low speed bit patterns from a device under test (DUT). The logic may further include a bit replication logic block that replicates bits such that the output of the device's high speed transceiver looks like a low speed signal to the DUT. The device, therefore, can communicate with the DUT at both the high and low speeds without the need for intermediate hardware.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.