High volume system level testing of devices with pop structures
US10656200B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2017 |
| Grant date | May 19, 2020 |
| Priority date | — |
| Expiry date | Jan 25, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2893
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A high volume system level testing of devices with POP structures such as POP memories includes a POP array that includes floating nests that can adjust in the XY direction in order to align individually with respective pads found on the DUTs. The floating nests also include a mechanically fixed PCB that is fixed to the nest and can either mate to a memory contactor array that can accept an unattached POP device such as a memory or can include an attached memory in order to accommodate different POP requirements. In a method, the POP array includes a number of floating nests with memory loaded are aligned and presented to their respective DUTs just prior to testing the combined DUT and POP memory assemblies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.